Method for forming shallow trench isolations

ABSTRACT

A method for forming shallow trench isolations includes the steps of defining a wafer substrate, forming a silicon dioxide insulating layer on the substrate, depositing a silicon nitride layer on the silicon dioxide insulating layer, and forming at least one trench in the substrate through the silicon dioxide and silicon nitride layers. The method also includes the steps of depositing a silicon dioxide layer over the silicon nitride layer and in the trench, removing the silicon dioxide layer deposited over the silicon nitride layer, anisotropically etching the silicon dioxide layer to produce silicon dioxide sidewalls in the trench contiguous with the silicon nitride layer, isotropically etching to remove the sidewalls and removing the silicon nitride layer.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention pertains in general to shallow trench isolationsin a semiconductor device and, more particularly, to a method of formingsubstantially planar shallow trench isolations.

[0003] 1. Description of the Related Art

[0004] Shallow trench isolations (“STIs”) are used for device isolationin an integrated circuit. A conventional process of forming STIs beginsby defining a wafer substrate. An insulating layer of silicon dioxide isthen grown over the substrate, followed by depositing a layer of siliconnitride over the insulating layer. After shallow trenches are patternedand formed in the device substrate and through the insulating layer andthe silicon nitride layer, silicon dioxide is deposited, filling thetrenches and in the process forming a layer over the silicon nitridelayer. Silicon dioxide deposited over the silicon nitride layer isremoved, usually with chemical-mechanical polishing (“CMP”), to obtain asubstantially planar surface.

[0005] However, the silicon dioxide layer, deposited by a conventionallow pressure chemical vapor deposition (“LPCVD”) technique, is oftenthicker at the wafer edge, or “bowl-shaped.” As a result, the CMPprocess that leaves a substantially planar surface would also leavesilicon dioxide residues over the silicon nitride layer at the waferedge. If the residues are not removed, they act as a mask and preventsubsequent removal of the silicon nitride layer. If, however, the waferis intentionally over-polished during the CMP process to remove thesilicon dioxide at the wafer edge, the STIs closer to the center of thewafer will become bowl-shaped, i.e., non-planar, which may impedesubsequent STI formation process steps.

[0006] The process continues by etching back the silicon dioxide in thetrenches using a buffered oxide etch (“BOE”), a type of isotropicetching, to yield a planar surface. The silicon nitride layer serves asan etch stop for the BOE. This is followed by the removal of the siliconnitride layer with hot phosphoric acid H₃PO₄.

[0007] This conventional STI formation process, however, often leavesmicro-trenches that result in nonplanarity of the oxide surface, at theinterface between the silicon dioxide in the trenches and the devicesubstrate. The micro-trenches present an impediment to subsequent deviceformation processes. The formation of micro-trenches is largely due tothe BOE that leaves undesired micro-trenches between the etched materialand etch-stop. When the etch-stop, i.e., silicon nitride, is stripped,the micro-trenches remain.

[0008]FIG. 1 illustrates the resulting structure. Referring to FIG. 1,micro-trenches 2 are formed at the interface between silicon substrate 4and silicon dioxide 6 in shallow trenches 8.

SUMMARY OF THE INVENTION

[0009] Accordingly, the present invention is directed to a method offorming a planar shallow trench isolation structure that substantiallyobviates one or more of the problems due to limitations anddisadvantages of the related art.

[0010] Additional features and advantages of the invention will be setforth in the description which follows, and in part will be apparentfrom the description, or may be learned by practice of the invention.The objectives and other advantages of the invention will be realizedand attained by the structures and methods particularly pointed out inthe written description and claims hereof, as well as the appendeddrawings.

[0011] To achieve these and other advantages, and in accordance with thepurpose of the invention as embodied and broadly described, there isprovided a method for forming planar shallow trench isolations in awafer substrate having a silicon dioxide insulating layer disposed overthe substrate and a silicon nitride layer disposed over the silicondioxide insulating layer to form a substrate-insulator-silicon nitridestack. A surface of the substrate-insulator-silicon nitride stack isplanar and has a plurality of trenches filled with silicon dioxide. Themethod includes the steps of anisotropically etching the silicon dioxidelayer to produce in the trenches silicon dioxide having sidewallscontiguous with the silicon nitride layer, and isotropically etching toremove the silicon dioxide sidewalls such that the silicon dioxide inthe trenches is planar with the silicon dioxide insulating layer.

[0012] In another aspect, the step of isotropically etching includes astep of performing a buffered oxide etch.

[0013] In yet another aspect, the step of anisotropically etchingincludes a step of etching with faster etch rate at the edge of thewafer.

[0014] Also in accordance with the invention, there is provided a methodfor forming shallow trench isolations. The method includes the steps ofdefining a wafer substrate, forming a first insulating layer on thesubstrate, and depositing a second insulating layer on the firstinsulating layer wherein the first insulating layer is a differentmaterial than the second insulating layer. The method also includes thesteps of forming at least one trench in the substrate through the firstand second insulating layers, depositing a third insulating layer overthe second insulating layer and in the trench wherein the thirdinsulating layer is the same material as the first insulating layer andremoving portions of the third insulating layer deposited over thesecond insulating layer to obtain a planar surface on the secondinsulating layer. The method additionally includes the steps ofanisotropically etching the third insulating layer such that the thirdinsulating layer inside the trench has sidewalls contiguous with thesecond insulating layer, isotropically etching to remove the sidewallssuch that the third insulating layer in the trench is planar with thefirst insulating layer, and removing the second insulating layer.

[0015] In one aspect of the invention, the step of removing the siliconnitride layer includes a step of removal with hot phosphoric acid.

[0016] In another aspect, the step of forming a second insulating layerincludes a step of depositing silicon nitride.

[0017] It is to be understood that both the foregoing generaldescription and the following detailed description are exemplary andexplanatory and are intended to provide further explanation of theinvention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings, which are incorporated in andconstitute a part of this specification, illustrate embodiments of theinvention and, together with the description, serve to explain theobjects, advantages, and principles of the invention.

[0019] In the drawings:

[0020]FIG. 1 shows a cross-sectional view of a silicon substrate havingmicro-trenches between STIs and the device substrate; and

[0021] FIGS. 2A-2F are cross-sectional views of the formation of STIs inaccordance with the method of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] A method in accordance with the present invention is explainedwith reference to FIGS. 2A-2F. Referring to FIG. 2A, a process of thepresent invention begins by defining a wafer substrate 12. After a firstlayer of insulating material 14 such as silicon dioxide is grown onsubstrate 12, a second insulating layer 16 is deposited over insulatinglayer 14. Insulating layer 16 may be silicon dioxide, silicon nitride orsilicon oxynitride, but, for purposes of the present invention, cannotbe the same material as insulating layer 14. In a preferred embodiment,insulating layer 14 is silicon dioxide and insulating layer 16 issilicon nitride. A photoresist 18 is then applied over insulating layer16. Photoresist 18 is patterned to form shallow trenches in substrate 12through insulating layer 14 and insulating layer 16. Photoresist 18 isthen stripped.

[0023] Referring to FIG. 2B, a plurality of shallow trenches 20 areformed in substrate 12 through insulating layers 14 and 16. A thirdlayer 22 of insulating material is then deposited, filling shallowtrenches 20 and in the process forming a layer over second insulatinglayer 16. Third insulating layer 22 is a different material than secondinsulating layer 16 but is the same material as first insulating layer14. In a preferred embodiment, third insulating layer 22 is silicondioxide. As shown in FIG. 2C, third insulating layer 22 deposited oversecond insulating layer 16 is removed either with CMP or etched back toobtain a planar surface. As a result, third insulating layer 22 fillstrenches 20.

[0024] Third insulating layer 22, e.g., silicon dioxide, deposited witha conventional “LPCVD” technique is often thicker at the wafer edge andthinner at the center of the wafer as previously described. Thesubsequent CMP process may be adjusted to produce a substantially planarsurface but this process would leave silicon dioxide residue over thesecond insulating layer at the wafer edge. As discussed above, if theresidue is not removed, it acts as a mask and prevent subsequent removalof the second insulating layer. An alternative is to completely removethe deposited silicon dioxide on the wafer edge by excessive polishingor etching, but this will leave a wafer thinner at the center than itsedge. For purposes of the present invention, the alternative of leavinga substantially planar surface with silicon dioxide residue over thewafer edge is preferred.

[0025] The present invention continues by removing a portion of thethird insulating layer remaining in the trenches. By dry etching oranisotropic etching, and with second insulating layer 16 as anetch-stop, the silicon dioxide resides at the wafer edge is removed. Asa result, a bowl-shaped third insulating layer 22 remains in thetrenches. This is shown in FIG. 2D. The shape of third insulating layer22 is characterized by sidewalls 24 at the interface between thirdinsulating layer 22 and second insulating layer 16. In a preferredembodiment, sidewalls 24 are contiguous with first and second insulatinglayers 14 and 16, respectively. If sidewalls 24 are not contiguous withsecond insulating layer 16 or far exceeds the thickness of secondinsulating layer 16, non-planar STIs will be formed as a result.

[0026] In addition, the anisotropic etch of the present invention may beadjusted such that it has a faster etch rate at the wafer edge than atthe wafer center. This adjustment ensures that residues of the thirdinsulating layer on the wafer edge left over after the CMP planarizationprocess will be removed so that they do not impede the subsequentremoval of the second insulating layer.

[0027] After the anisotropic etch, the method of the present inventioncontinues with isotropic etching to remove sidewalls 24 to obtain aplanar surface in the trenches. As shown in FIG. 2E, the remaining thirdinsulating layer 22 is planar with first insulating layer 14. Thisisotropic etch may be accomplished with BOE. In a final step shown FIG.2F, second insulating layer 16 is then removed. If second insulatinglayer 16 is silicon nitride, hot phosphoric acid H₃PO₄ may be used forits removal, leaving a layer of substantially planar surface.

[0028] Referring to FIG. 2F, the resulting structure is a semiconductorwafer that includes STIs and a pad oxide on the surface of the wafer.The surface of the wafer is planar. Specifically, substrate 12 includesa plurality of STIs, formed by third insulating layer 22 in trenches 20.The surface of substrate 12 is planar and free of micro-trenches.

[0029] It will also be apparent to those skilled in the art that variousmodifications and variations can be made in the disclosed process andproduct without departing from the scope or spirit of the invention.Other embodiments of the invention will be apparent to those skilled inthe art from consideration of the specification and practice of theinvention disclosed herein. It is intended that the specification andexamples be considered as exemplary only, with a true scope and spiritof the invention being indicated by the following claims.

What is claimed is:
 1. A method for forming planar shallow trenchisolations in a wafer substrate having a silicon dioxide insulatinglayer disposed over the substrate and a silicon nitride layer disposedover the silicon dioxide insulating layer to form asubstrate-insulator-silicon nitride stack, a surface of thesubstrate-insulator-silicon nitride stack being planar and having aplurality of trenches filled with silicon dioxide, comprising the stepsof: anisotropically etching the silicon dioxide layer to produce in thetrenches silicon dioxide having sidewalls contiguous with the siliconnitride layer; and isotropically etching to remove said silicon dioxidesidewalls such that the silicon dioxide in the trenches is planar withthe silicon dioxide insulating layer.
 2. The method as claimed in claim1 wherein said step of isotropically etching comprises a step ofperforming a buffered oxide etch.
 3. The method as claimed in claim 1wherein said step of anisotropically etching comprises a step of etchingwith faster etch rate at the edge of the wafer.
 4. A method for formingshallow trench isolations, comprising the steps of: defining a wafersubstrate; forming a first insulating layer on said substrate;depositing a second insulating layer on said first insulating layer,said first insulating layer being a different material than said secondinsulating layer; forming at least one trench in said substrate throughsaid first and second insulating layers; depositing a third insulatinglayer over said second insulating layer and in said trench, said thirdinsulating layer being the same material as said first insulating layer;removing portions of said third insulating layer deposited over saidsecond insulating layer to obtain a planar surface on said secondinsulating layer; anisotropically etching said third insulating layersuch that said third insulating layer inside said trench has sidewallscontiguous with said second insulating layer; isotropically etching toremove said sidewalls such that said third insulating layer in saidtrench is planar with said first insulating layer; and removing saidsecond insulating layer.
 5. The method as claimed in claim 4 whereinsaid step of isotropically etching comprises a step of performing abuffered oxide etch.
 6. The method as claimed in claim 4 wherein saidstep of anisotropically etching comprises a step of etching with afaster etch rate at the edge of said substrate than the center of saidsubstrate.
 7. The method as claimed in claim 4 wherein said step ofremoving said silicon nitride layer comprises a step of removal with hotphosphoric acid.
 8. The method as claimed in claim 4 wherein said stepof forming a first insulating layer comprises a step of forming a layerof silicon dioxide.
 9. The method as claimed in claim 4 wherein saidstep of forming a second insulating layer comprises a step of depositingsilicon nitride.
 10. The method as claimed in claim 4 wherein said stepof forming a first insulating layer on said substrate comprises a stepof forming a layer of silicon dioxide by oxidation.